1. Field of the Invention
The present invention relates in general to power supplies for memory arrays, and more particularly to circuitry for supplying power to the gate of flash electrically erasable programmable read-only memory (EEPROM) cells utilized in multi-density and low voltage supply memory arrays.
2. Description of the Related Art
Because memory arrays in the past included array cells with threshold values programmed to represent two or more states separated by a wide margin, a power supply signal for the memory array, V.sub.SUPP, also typically referred to as V.sub.CC or V.sub.DD, was adequate to supply power directly to the gate of the array cell to determine the state stored.
FIG. 1 shows circuitry utilized for providing V.sub.SUPP to the gates of multi-density flash EEPROM cells in a memory array 102. Further details for providing a multi-density memory array can be found in U.S. Pat. No. 5,218,569 by Banks entitled "Electrically Alterable Non-Volatile Memory With N-Bits Per Memory Cell", incorporated herein by reference. FIG. 1 further includes a reference array 104 with reference cell gates powered directly by V.sub.supp. Details for providing a programmable reference array such as reference array 104 can be found in U.S. patent application Ser. No. 08/160,582 entitled "Programmed Reference" by the present inventors filed on Dec. 1, 1993, incorporated herein by reference.
Along with the memory array 102 and reference array 104, FIG. 1 includes a reading power supply 105 and a programming power supply 106 which provide power to a wordline decoder 108. During application of a READ signal, reading power supply 105 supplies V.sub.SUPP to wordline decoder 108 as a signal VPX. During application of a program signal (PGM), a boosted signal greater than V.sub.SUPP is supplied by programming power supply 106 to wordline decoder 108 as a signal VPX. The program signal PGM is applied to increase electrons stored on the floating gate of a memory cell. During application of an erase signal, a large negative voltage is applied by circuitry (not shown) to the gates of the array cells of memory array 102. The erase voltage is applied to remove electrons from the floating gate of a memory cell. The wordline decoder 108 decodes the wordline address to select VPX to one of wordlines WL0-WLN. Each. wordline WL0-WLN is connected to the gates of a row of array cells in memory array 102. Bitlines of cells in a row are connected to corresponding array cells in the remaining rows to provide a memory array output to sense amplifiers 112.
In FIG. 1, V.sub.SUPP is supplied directly to the gates of the reference cells of reference array 104. However, utilizing nonprogrammable reference cells, V.sub.SUPP can be applied through wordlines WL0-WLN to the gates of the reference cells. In FIG. 1, the programmable reference cells are not connected through the wordlines because a large negative gate voltage applied over wordlines WL0-WLN during erase would erase any connected reference cell.
Reference array 104 is shown containing groups of four cells as required for a 3/2 density memory, although more or less cells may be utilized for different densities. FIG. 2 shows representative threshold voltage values for reference cells of a single density, 3/2 density and double density memory array. For the 3/2 density reference array 104, two cells in a group of four cells provide reference states A and B utilized to read the state of a memory cell, while the remaining two cells provide the 0 0 and 0 0.5 states utilized to program a threshold of an array cell in memory array 102. Note that the 1 1 state is the unprogrammed state and does not require a reference.
Multiplexers 110-0 through 110-N are each connected to the drains of respective groups of four reference cells in reference array 104. A VERIFY signal is supplied to each of the multiplexers which in a high state indicates the READ signal is being applied to verify if the array cell has been fully programed. If the VERIFY signal is high, the multiplexer will couple the references storing the 0 0 and 0 0.5 states to sense amplifiers 112 to enable determination if an array cell has been properly programed. If the VERIFY signal is low, the multiplexer will couple the references storing the reference state A and B values to sense amplifiers 112 to enable reading of an array cell.
Sense amplifiers 112 individually compare the array cell bitline drain currents from memory array 102 to respective reference cell drain currents output from multiplexers 110-0 through 110-N to determine the state of each selected array cell with respect to each reference. Decoder 114 then decodes the output of the two sense amplifiers for each selected array cell to provide an output corresponding to the state stored by each selected array cell.
By utilizing programmable multi-density memory arrays, the density of data stored by each memory cell can be increased even beyond double density. However, as shown in FIG. 2, as the density is increased, the working margin between reference levels decreases. For instance, utilizing single density, the margin between the 0 state and the reference state is (4.00 V-2.9 V=1.10 V.) With 3/2 density, the margin is reduced by 50% (4.00 V-3.45 V=0.55 V), and for double density the margin is reduced to 0.33 V. The working margin is also reduced in low voltage supply memories because with a reduction in V.sub.SUPP, the available range of thresholds detectable from an array cell is reduced.
In a multi-density or low voltage supply memory, a low working margin can result in increased read errors due to the different rates at which cells lose or gain charge from their floating gates over time.
Further, with a low working margin, when V.sub.SUPP varies, cell to cell mismatches can contribute to read errors. Mismatches include capacitive coupling differences between memory cells. Mismatches further include transconductance differences between array cells resulting from their different locations along a wordline. Further, with a low working margin, variations in V.sub.SUPP can result in more read errors due to the phase difference between V.sub.SUPP as separately supplied to the memory array 102 and the reference array 104.